The present invention is related in general to the field of electronic circuits, and more specifically to an apparatus and method for improved damping control of a loop filter included in a phase locked loop (PLL).
A traditional PLL is a well-known electronic circuit used in many semiconductor devices. PLL circuits are typically used for frequency/timing control in a variety of applications including clocks, frequency multipliers, demodulators, tracking generators, and clock recovery circuits. A PLL is a closed loop feedback control circuit which provides an output signal that is locked in phase and frequency of an input signal used as a reference. FIG. 1 is a simplified block diagram of a traditional type II phase locked loop 100, according to prior art. The PLL 100 includes a phase frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter 130, a voltage-controlled oscillator (VCO) 140, and an optional divider 150. The PFD 110 compares a feedback signal 112 received from the divider 150 with a reference signal 102 and generates an error signal 104 which is proportional to the magnitude of the phase/frequency difference between them. The error signal 104 is provided to the CP 120. The CP 120 provides a current output to control the charge stored in the loop filter 130, thus converting the output of the PFD 110 to a control voltage input 106 recognizable by the VCO 140. The loop filter 130 filters out undesirable higher frequencies, glitches, spurious noise, spurs and the like from the CP 120 current output signal. The VCO 140 generates an output frequency signal 108 proportional to the control voltage input 106. The output frequency signal 108 may be optionally further divided down by the divider 150 before being fed back to the PFD 110. When the PLL 100 is “locked”, there is a constant phase difference (usually zero) between the feedback signal 112 and a reference signal 102 and their frequencies are matched.
It is well known that performance and stability of the traditional PLL is often controlled by the following PLL parameters: 1) natural frequency or loop bandwidth (Wn), 2) damping factor (zeta), and 3) the 3 dB bandwidth. The 3 dB bandwidth is a measure of the frequency range within which the PLL is able to track frequency changes of the reference signal 102. For a PLL loop having a large damping factor zeta, the 3 dB bandwidth is approximately equal to 2*zeta*Wn. The damping factor zeta determines the responses of phase or frequency error steps applied to the input of the PLL. Zeta may be adjusted to achieve a fast response or small overshoot and minimum phase noise bandwidth. If zeta is very small, a large overshoot and an increased phase jitter may occur. If zeta is too large, the response may become sluggish resulting in increased time to lock the PLL. Many PLL loops may be configured to have a damping factor typically varying between approximately 0.7 and approximately 2. The peaking of a loop is inversely proportional to the damping factor zeta. Many modern broadband communication system applications such as a Gigabyte Passive Optical Network (GPON) often specify a PLL having a small 3 dB bandwidth (e.g., 0.5 megahertz) and stringent peaking (e.g., less than 0.1 dB) specifications. Therefore, being inversely proportional, it is a challenge to minimize both 3 dB bandwidth and peaking specifications of a PLL.
The loop filter 130 may be implemented using passive components such as a passive resistor capacitor (RC) circuit or may be implemented using an active component such as an operational amplifier (OA or opamp) used in combination with an RC circuit. For simultaneous compliance with low bandwidth and low peaking specifications, a large value of a capacitor may be required to provide a lower zero frequency of the loop filter 130. However, a capacitor having a large value consumes a significant portion of silicon chip area. In some conventional loop filters, the large value for the capacitor may force the use of an off-chip fabricated component, e.g., use as an externally mounted capacitor component.
A known solution to improve control of bandwidth and peaking parameters of a PLL is to utilize a traditional dual path loop filter architecture (not shown) in which the charge pump current is split into two paths—a proportional path powered by a proportional charge pump and an integral path powered by an integral charge pump. The dual path PLL design enables bandwidth adjustment by controlling gain in the proportional path and enables damping adjustment by controlling gain in the integral path. However, the accuracy of controlling gain in each of the two paths, especially the integral path, is limited by various factors including inability to reduce integral charge pump current below a practical level (generation of very small charge pump current may result in dead zone, jitter and phase noise problems), device mismatch, process variation, and increased integral charge pump current error due to transistor current leakage. In addition, inclusion of a floating capacitor in the integral path often results in increasing the silicon area of the loop filter and the PLL.